62DAC · AD1862 NOS DAC · board at commit 342ad76

62DAC Signal Integrity Study

What on this board limits two AD1862s, and what to change to get their full 20-bit performance. Every number here comes from free tools run on the actual KiCad layout.

29 Oct 2026 openEMS 0.37 FDTD (Metal GPU) ngspice KiCad 10 pcbnew export numpy / scipy solvers Русская версия
Summary

Where the board stands

The layout is fundamentally sound: two solid ground planes, short summing nodes, decoupling within 2–3 mm of every AD1862 supply pin. The real limits are all about timing: how the Pico produces its sample clock, how the shared clock and latch lines are routed, and how the firmware drives them.

Change
The Pico's sample clock, if the PIO uses a fractional dividerThe SDK's 125 MHz system clock is not a whole multiple of 44.1 kHz, so a fractional PIO divider puts each LE edge up to one 8 ns tick early or late, in a repeating pattern. That alone is more than ten times the board's worst timing effect. The RP2040 can run at an exact multiple instead.
LE error 4–7 ns p-p
spurs −75 to −80 dBFS (10–20 kHz tone)
exact clock: none
Change
Shared CLK and LE lines split in a T right at the PicoWith fast edges the near DAC (U1) stalls on a shelf inside its switching band, and the tree rings at 405 MHz for about 20 ns. Noise on that shelf moves the LE edge, and in a NOS DAC the LE edge is the sample instant.
LE at U1: 3.8 ps per mV of noise
CLK at U1: 13.9 ps/mV
point-to-point: 0.35 ps/mV
Watch
CLK couples onto LE along the shared busHarmless if the clock is stopped when LE falls, which is also what the diyAudio builders converged on. Data lines pick up far less.
CLK → LE at the DAC: 51 mV (3 ns edge), 88 mV (1 ns)
CLK → data: ≤ 12 mV
Watch
Decoupling between 100 kHz and 5 MHzThe electrolytics' ESR sets a 0.2–0.5 Ω plateau with an anti-resonance near 4.5 MHz, where a Pico bit clock is likely to run.
peak 0.45 Ω at 4.5 MHz
with 10 µF X7R added: ~0.02 Ω
Good
Clock and latch edge integrity as built33 Ω series resistors with the RP2040's default 4 mA drive give clean, monotonic edges at both DACs. Even the worst drive setting tried cannot false-clock.
overshoot ≤ 0.03 V (3 ns edge)
worst ringback 2.24 V > VIH 2.0 V
Good
Digital coupling into the I/V summing nodesCharge injected per clock edge is a small fraction of one LSB held for one sample, even before the rising and falling edges cancel.
0.5–0.8 fC per CLK edge
1/90–1/50 of an LSB·sample
LE edge: 0.6–0.8 fC, ≈ −150 dB
Good
Ground planes and return pathsBoth inner planes are unbroken under every digital route; return current stays within about a millimetre of each trace. The DAC's signal-correlated ground current barely shifts the op-amp's reference.
0.6 µV per mA, DAC GND → op-amp +IN
(1 LSB at the output ≈ 2.7 µV)
Good
Audio-band supply impedanceBelow 20 kHz the board's decoupling is not the limit; the off-board regulator is.
≈ regulator Zout + 30 mΩ
What to change

Changes, ranked by benefit for effort

Firmware changes cost nothing and address the largest effect, so they come first. Each item says where the evidence comes from: simulated on this layout, diyAudio (post numbers in the forum's AD1862 thread, no. 354078), or datasheet.

  1. Run the PIO from an exact multiple of the sample rate

    Set clk_sys to 110.25 MHz for 44.1/88.2/176.4 kHz (PLL: REFDIV 2, FBDIV 147, post-dividers 4 and 2; VCO 882 MHz), or to 129.6 MHz for 48/96/192 kHz (VCO 1296 MHz, ÷5÷2). Write the PIO program so every sample takes exactly 2500 (or 2700) system clocks with an integer divider. Both clocks are within the RP2040's 133 MHz rating, and only firmware changes.

    With the SDK's 125 MHz and a fractional divider, LE edges wander by 4–7 ns in a fixed pattern, giving spurs of −75 to −80 dBFS on a 10–20 kHz tone. With the exact clock that error is zero; what remains is the PLL's random jitter, which the datasheet does not specify. Changing sample-rate family means re-locking the system PLL; USB runs from its own PLL and is unaffected. The DAC then sets the rate, so USB audio must run in asynchronous mode with a feedback endpoint.

    simulated (timing model) · RP2040 datasheet §2.18, §3.5.5

  2. Stop the clock before LE falls, and keep the bus static in silence

    Shift the 20-bit word right-justified, stop CLK, hold DATA, then drop LE 3–4 bit periods later. During silence, hold CLK, LE and DATA static. The PIO program can do this at no cost.

    The simulated 51–88 mV of CLK→LE crosstalk then never coincides with the LE edge, so the T-split's threshold shelf has no noise to turn into sample-time jitter. Builders on the thread measured a sample-rate residual of about 1 µA equivalent that disappears when the clocks stop.

    simulated · diyAudio #3957, #4277, #6513, #6533–6534

  3. Keep the RP2040 pads at slow slew and 4 mA drive (the defaults)

    A 3 ns edge cuts the T-split's jitter sensitivity at U1 from 13.9 to 1.15 ps/mV on CLK and from 3.8 to 1.1 ps/mV on LE. It also reduces CLK→LE crosstalk from 88 to 51 mV. Do not enable fast slew on these four pins.

    simulated (ngspice + openEMS)

  4. Give each DAC its own LE pin, and ideally its own CLK pin

    Route two Pico GPIOs instead of one, each through its own series resistor near the Pico. About 27 Ω suits 4 mA drive on these 67 Ω traces. PIO side-set toggles both pins on the same cycle, so the DACs stay in step. Both DACs then see a clean single ramp at 0.35 ps/mV, and the 405 MHz tree resonance disappears.

    simulated · 2 resistors + 2 short traces

  5. Re-time LE at the DACs from a low-jitter audio oscillator

    Feed a 45.1584 or 49.152 MHz audio oscillator (or half that) into GPIO20 (GPIN0, up to 50 MHz) and pace the PIO from it: either run clk_sys from it, or have the PIO wait on its edges. Put a dual D flip-flop (74LVC74 class) beside the DACs, clocked by the same oscillator, so each LE edge comes from the oscillator rather than from the Pico's PLL and output pins.

    Each half of the flip-flop drives one DAC over a short trace, which also removes the T-split. Assuming about 2 ps of oscillator jitter, the sample-time error stays below −135 dBFS even for a full-scale 20 kHz tone.

    simulated (timing model) · RP2040 datasheet §2.15 · diyAudio #870, #944, #1787

  6. Add 10 µF X7R next to each 100 nF on ±VL and ±VS

    This flattens the 0.2–0.5 Ω region and removes the 4.5 MHz anti-resonance; impedance from 200 kHz to 5 MHz drops to about 20 mΩ. It leaves a mild 0.3 Ω bump near 100 kHz, still well above the audio band.

    simulated (ngspice PDN model)

  7. Spend the effort on the regulators, not on more board capacitance

    Below 20 kHz the rail impedance is the regulator's own. Low-noise LDOs (LT3045/LT3094 class) are what builders used for their best results. Keep ferrite beads off the analog rails.

    simulated · diyAudio #893, #2819, #11631

  8. Put a GND via within 0.5 mm of each signal via

    The six vias on CLK, D_L and D_R currently have their nearest ground via 1.6–2.6 mm away. The return current visibly spreads at those layer changes.

    simulated (return-current map)

  9. Use C0G for the 47 pF caps, and leave room for a summing-node shunt

    C31, C36, C50 and C51 should be C0G. Optionally add a do-not-populate footprint for a 1–2 nF C0G shunt from the summing node to ground, as in the AD797 data sheet's AD1862 circuit. Builders disagree on its value.

    diyAudio #10842, #1970, #2716, #4960

  10. Leave the MSB trim unpopulated, and protect the supply order

    Trim only with an FFT at −60 dBFS; a mis-set trimmer adds 20–30 dB of odd harmonics. Because each rail has a removable jumper, add a Schottky so −VL can never go more negative than −VS.

    diyAudio #4770–4772, #10842 · datasheet abs. max.

1 · Method

How the board was simulated

The copper geometry comes straight from 62DAC.kicad_pcb through KiCad's own polygon engine: every track, pad, via barrel and filled zone, per layer. The stackup is JLC04161H-7628: 0.21 mm prepreg (εr 4.4) between each outer layer and its ground plane, and a 1.065 mm core.

  • Full-wave: openEMS 0.37 FDTD, built from source and run on the M1 GPU through Metal. The model covers the digital bus, both AD1862 sockets and both I/V stages: a 43 × 65 mm crop, 11.2 million cells. All 31 capacitors in that area are series R‑C elements. The driven line has a 73 Ω source (33 Ω series resistor + ~40 Ω RP2040 pad); quiet lines have 73 Ω at the Pico end; each DAC input is 5 pF; each I/V summing node is 50 Ω.
  • Circuit: ngspice transmission-line models of the CLK and LE trees for sweeps; a PDN model with the measured cap-to-pin distances.
  • Sample clock: a timing model of the RP2040 PIO divider (datasheet §3.5.5) and PLL limits (§2.18), with the NOS output spectrum for each clocking scheme.
  • Ground drop: a resistive solver on the rasterised In1 + In2 fill, tied by every GND via and pin barrel.

Validation

0.2 mm trace on F.Cu over In1Z0εeffNote
Closed form, zero-thickness strip (Hammerstad–Jensen)72.8 Ω3.16reference for the FDTD sheet model
Closed form, 35 µm copper67.0 Ω3.19what the real board has
openEMS, 0.2 mm cells, lines on the edges42.5 Ω3.52too coarse
openEMS, 0.1 mm cells62.0 Ω3.26converging
openEMS, 0.15 mm with the ⅓–⅔ edge rule (used for the board)73.8 Ω3.19within 1.4 % of the sheet reference

The ngspice and openEMS CLK waveforms agree on the shape: overshoot 0.12–0.18 V at a 1 ns edge, the same threshold shelf at U1, and the same ~405–430 MHz ringing. The tree rings for about 20 ns, longer than is practical to simulate, so each probe's tail after the pulse was extended with the board's own natural modes, fitted jointly across all probes. Tail-fit error is 2–11 % on most probes and 23 % on IOUT_L. Treat the coupling figures below as ±25 %.

Copper of F.Cu over In1 and B.Cu over In2 with the four digital nets highlighted
What the solver sees. Grey is the GND fill on In1 (left) and In2 (right). CLK is red, LE blue, D_L green, D_R purple, the I/V summing nodes orange. No digital route crosses a gap in its reference plane.
2 · Sample clock

The Pico's clock sets the sample instants

In a non-oversampling DAC each sample reaches the output the moment LE falls, so any error in when LE falls becomes an amplitude error. The PIO program generates LE, and the PIO runs from the system clock through a 16.8 fractional divider. The datasheet describes it as first-order delta-sigma: to reach a non-integer ratio it stretches some periods from n to n+1 system clocks. At the SDK's default 125 MHz, 44.1 kHz needs 2834.47 clocks per sample, so the LE edges land on a grid of 8 ns ticks in a repeating pattern.

LE timing error per sample with a 125 MHz system clock and a fractional PIO divider
LE timing error with the SDK's 125 MHz clock and a fractional divider, for PIO programs of 64 and 96 cycles per sample. The pattern repeats every 2 or 8 samples and spans 4–7 ns.

The model moves each step of the NOS staircase by its LE error and computes the output spectrum for a −1 dBFS tone. The output is quantised to 20 bits, so the AD1862's own floor is visible for comparison.

Output spectra of a 10 kHz tone for four clocking schemes
Output spectrum for a 10 kHz tone under four clocking schemes. The fractional divider adds spurs at −80 to −92 dBFS. With an exact clock only random noise remains, below the 20-bit floor.
Clock schemeLE error1 kHz tone10 kHz20 kHzRate error
125 MHz, fractional divider, 64 cycles/sample4 ns p-pout of band*−80 dBFS−76 dBFS−12 ppm
125 MHz, fractional divider, 96 cycles/sample7 ns p-p−98 dBFS−79 dBFS−75 dBFS−56 ppm
Exact 110.25 MHz, assumed 30 ps random30 ps rms−136 dBFS−117 dBFS−113 dBFS0
Audio oscillator + flip-flop, ~2 ps2 ps rms−159 dBFS−140 dBFS−137 dBFS0

Values are the total jitter error from 20 Hz to 20 kHz relative to full scale, for a −1 dBFS tone at 44.1 kHz. * With 64 cycles the pattern alternates every sample, so a 1 kHz tone's error lands at 21.05 kHz, just above the audio band. Where the spurs fall depends on firmware details.

With an exact clock, the remaining random jitter comes from the PLL and the Pico's output pins. The datasheet gives no figure for it, so the chart below shows what any amount costs. Staying under the AD1862's ~−120 dB floor takes about 10 ps RMS for a full-scale 20 kHz tone, or about 160 ps at 1 kHz. A good audio oscillator re-timed by a flip-flop sits at a few picoseconds.

Error relative to full scale versus RMS sample-instant jitter, with the cases from this study marked
Error from random sample-instant jitter for a full-scale tone in a NOS DAC, 2·sin(πf/fs)·fs·σ. The red points are the deterministic cases from this study.
3 · Edges

Clock and latch edges at the AD1862 pins

CLK and LE each leave one Pico pin, pass one 33 Ω resistor, then split. CLK runs 27.8 mm to U1 and 80.2 mm to U2; LE runs 31.9 mm and 65.3 mm. The near DAC therefore gets its edge in two steps: half the swing arrives at once, and the rest waits for the reflection from the far branch. With a fast edge, that step lands inside the 0.8–2.0 V input threshold band.

Rising edges of CLK and LE at both DACs for shared T-split and one-pin-per-DAC routing, at 1 ns and 3 ns edges
Shared pin with T-split (solid) vs one pin per DAC (dashed). Grey band: 1.2–1.8 V, where a TTL-threshold CMOS input actually switches. With 1 ns edges the U1 curves pause in the band; point-to-point gives a single clean ramp.
Line · edgeTopologyTime in 1.2–1.8 V, U1Timing shift per mV of noise, U1U2
CLK · 1 nsshared, T-split (as built)1.14 ns13.9 ps/mV0.47 ps/mV
LE · 1 nsshared, T-split (as built)0.74 ns3.84 ps/mV0.51 ps/mV
CLK or LE · 1 nsown pin per DAC, 27 Ω0.20 ns0.35 ps/mV0.35 ps/mV
CLK · 3 nsshared, T-split (as built)0.57 ns1.15 ps/mV1.17 ps/mV
LE · 3 nsshared, T-split (as built)0.57 ns1.09 ps/mV1.19 ps/mV
CLK or LE · 3 nsown pin per DAC, 27 Ω0.55 ns0.92 ps/mV0.92 ps/mV

What this means in audio terms. Suppose 50 mV of data-correlated noise sits on LE while it falls at U1 with fast edges. That moves the sample instant by about 190 ps, which for a full-scale 20 kHz tone is an error near −96 dBFS, far above the AD1862's ~−120 dB floor. Point-to-point routing brings that to about −116 dBFS. A stopped clock removes the noise source itself.

openEMS CLK waveforms at both DAC pins and crosstalk on LE and data lines for 3 ns and 1 ns edges
openEMS, full board, CLK driven. Top: CLK at both DAC pins for a 20 ns pulse. Bottom: what appears on the quiet lines. LE at the DACs picks up 51 mV (3 ns edge) or 88 mV (1 ns edge); D_L and D_R stay at or below 12 mV.
ngspice CLK waveforms for series resistors 0, 33 and 68 ohm
Series resistor sweep (ngspice, 4 mA drive). 33 Ω is a good value. At 8–12 mA drive with 0–10 Ω the far DAC would ring by ±0.8–1.8 V. Across every combination tried (2–12 mA, 0–100 Ω) the first ringback never dropped below 2.24 V, so the edges cannot double-clock.
4 · Impedance

TDR and input impedance of the CLK tree

Looking in from the 33 Ω resistor, the driver sees 26–46 Ω for the first few centimetres: the two 67 Ω branches in parallel, pulled lower by the vias and DAC pins. The input impedance has sharp anti-resonances at 405 MHz and about 930 MHz. At those frequencies the source can't absorb energy, which is why the tree keeps ringing. Spatial resolution of this TDR is about 25 mm, set by the 1.4 GHz bandwidth of the run.

TDR impedance over distance and input impedance over frequency for the CLK net
Left: impedance over distance from a 300 ps, 50 Ω step. Right: impedance seen by the driver from 6 MHz to 1.4 GHz.
5 · Coupling

How much digital noise reaches the analog side

The I/V summing node (AD1862 pin 11 to OPA134 pin 2) is only 3.4 mm long on each channel, and it sits away from the bus. One CLK pulse pushes 0.15–0.34 µA peak into it. The net charge per edge is 0.5 fC on the left channel and 0.7–0.8 fC on the right. One LSB held for one 44.1 kHz sample is 43 fC. Assume 32 clock edges per sample that all add up instead of cancelling in rising/falling pairs. The result is about 1 nA of average current, roughly −120 dB below the ±1 mA full scale, which is the AD1862's own noise floor. In practice the pairs largely cancel.

Current injected into both I/V summing nodes by one CLK pulse
Current into each summing node during one 20 ns CLK pulse (3 ns edges). L and R have opposite sign because of where each trace runs relative to the bus.

With LE driven instead

LE's falling edge is the instant the AD1862 updates its output, so a second full-board run drove LE and kept CLK quiet. The LE edge injects 0.6 fC into the left summing node and 0.7–0.8 fC into the right. It happens once per sample and is the same every sample, so it's independent of the data. As an average current it comes to about 35 pA, around −150 dB below full scale.

LE in turn puts 55 mV (3 ns edge) or 89 mV (1 ns edge) onto CLK at U1. That's far below the ~1.4 V switching point, so it cannot clock in a false bit. The 1 ns plot also shows the T-split shelf on LE's falling edge at U1, near 1.65 V. That's the edge that latches the DAC.

openEMS LE waveforms at both DAC pins and crosstalk on CLK and data lines
openEMS, full board, LE driven. Top: LE at both DAC pins. Note U1's falling edge with a 1 ns source edge (right, near 23 ns). Bottom: pickup on CLK and the data lines.
Current injected into both I/V summing nodes by one LE pulse
Current into each summing node during one LE pulse (3 ns edges).
6 · Fields

Where the CLK energy actually goes

Animation of the vertical electric field under F.Cu as a CLK pulse propagates
Wave propagation. Ez in the prepreg under F.Cu as one pulse leaves the series resistor, splits, and reflects from both DACs (60 frames, about 5 ns). The B.Cu section of the U2 branch is hidden under the plane in this view.
Return current density on the In1 ground plane at 50, 100, 200 and 400 MHz
Return current on In1 (tangential H just above the plane). It stays within about 1 mm of the trace at every frequency and spreads only at the two CLK layer-change vias, where it must find a GND via to reach In2.
Near-field magnetic field 1 mm above the board at 50 to 400 MHz
Near-field |H| 1 mm above the board, relative to 1 V at the source. The strongest area is the series-resistor and via cluster at the lower left. These maps are for locating sources; they are not an absolute radiated-emission prediction.
7 · Ground

Ground voltage drop from the DAC's own current

The R‑2R ladder returns signal-dependent current through AD1862 pins 9 and 12. Any plane voltage between those pins and the op-amp's ground reference adds directly to the output. With 1 mA flowing from each DAC's ground pins to the supply connector J1, the difference is 0.59 µV (left) and 0.60 µV (right). That's about 0.2 LSB per mA at the output, so the plane is not a limit.

Potential on the In1 ground plane with 1 mA from each DAC's ground pins to J1
Potential on In1, 1 mA from U1 (left) or U2 (right) to J1, in µV. Solved on the real filled copper of In1 and In2 (0.5 oz), coupled through every GND barrel.
8 · Supplies

Decoupling seen from each AD1862 supply pin

Every supply pin has a 100 nF within 2.0–2.6 mm and a 47–100 µF electrolytic within 4–7.5 mm. Above 10 MHz the curve is set by the DIP socket and lead inductance (about 4 nH), which no board change can remove. Between 100 kHz and 5 MHz the electrolytics' ESR dominates, with an anti-resonance against the 100 nF near 4.5 MHz. A 10 µF X7R beside each 100 nF fixes that band.

Impedance at the die for all eight AD1862 supply pins, plus upgrade variants
|Z| at the die. Left: all four U1 supply pins as built. Right: U2 pins, plus the +VL pin with a 10 µF X7R added (brown), and with a polymer bulk cap as well (pink). The regulator is modelled as 30 mΩ + 300 nH of wiring.
9 · Limits

Assumptions to keep in mind